Recent years have witnessed phenomenal advances in the packing density of semiconductor chips involving further miniaturization of gate lengths. The trend has been making it necessary to define mask patterns of which the unit is smaller than the size of the wavelength of light for use by photolithography machines in transferring the patterns from the mask to the wafer.
Accurate definition of mask patterns having line widths less than the wavelength of light is generally implemented using OPC (optical proximity correction), a collection of techniques for correcting beforehand the shape of mask patterns, to allow for pattern deformations on the wafer caused by the so-called optical proximity effect. This collection of OPC techniques is also called PPC (process proximity effect correction). A typical OPC tool of this type is rule-based OPC.
Rule-based OPC is implemented as follows: a test-use mask pattern is prepared using test patterns representing all patterns that are permitted by design. The test patterns are transferred through the mask pattern onto the wafer for pattern etching, whereby a test-use wafer is produced.
The pattern geometry on the test-use wafer is then measured. The measured data, together with design data from the test-use mask pattern, are used as a basis for generating rule-based OPC, i.e., a collection of design rules for determining bias data to be added to mask pattern design data. The mask pattern is then corrected using the rule-based OPC. The correction takes place at a mask pattern layout stage in the CAD process. The mask fabricated through OPC is called the OPC mask.
Apart from rule-based OPC, there is another set of corrective techniques called simulation-based OPC.
This type of proximity effect correction involves generating a simulation-based OPC model (also called a kernel or a process model) that represents a pattern transfer process allowing for the optical proximity effect based on the measurements of a limited number of test patterns prepared beforehand. Differences in shape between the mask pattern and the pattern geometry transferred through the mask pattern onto the wafer are simulated by the simulation-based OPC model. The results of the simulation are used to correct the mask pattern.
Today, the ever-finer structures of gate patterns are highlighting so-called space dependency, a phenomenon in which the line widths of gate patterns are significantly affected by pattern-to-pattern spacing, i.e., by the fluctuating distances or spaces between the gate patterns and their adjacent patterns. This typically leads to a deterioration in so-called line width controllability of the gate patterns.
Under these circumstances, what is important is precisely to analyze how viable line width controllability is in evaluating the above-mentioned rule-based OPC and simulation-based OPC model.
Conventionally, line width controllability is analyzed for viability as follows: an evaluation-use mask is initially produced based on rule-based OPC or on a simulation-based OPC model. An evaluation-use wafer is then fabricated using the evaluation-use mask. The line widths of gate patterns on this wafer are measured and checked for errors and deviations with respect to space dimensions.
Since there exist a huge number of gate patterns on the evaluation-use wafer, it is impossible in practice to measure the line widths of all these patterns. Instead, some of the gate patterns are selected and measured for line widths. The trouble is that it is difficult to determine whether such selectively measured data are valid in representing the gate patterns on the evaluation-use wafer. As a result, the line width controllability of evaluation-use wafers has often been lacking in validity when evaluated.
It is therefore an object of the present invention to overcome the above and other deficiencies of the prior art and to provide methods for evaluating rule-based OPC and a simulation-based OPC model by which to determine line width controllability with precision.